The present invention is related to logic circuits that are able to provide valid output logic signals in the presence of a harsh radiation environment as is experienced in outer space.
When energetic heavy ions, like those found in space environments, collide with CMOS logic circuits, a transient current spike is introduced into the circuitry that can lead to parametric or even functional failures. The introduction of an undesirable current spike due to ionizing radiation is known as a Single Event Transient (SET).
One solution known in the art is referred to as Triple Mode Redundancy (TMR), which requires triple redundancy in at least portions of the circuit, followed by a voting circuit that returns the result common to two or more of the three redundant circuits. While the TMR solution effectively reduces the effects of transient spikes and improves circuit performance in high-radiation environments, it does so at the penalty of increased integrated circuit die area and corresponding cost. The increased integrated circuit die area can be triple or more that of an ordinary logic circuit.
What is desired is a logic circuit that can be fabricated in a cost efficient manner, but can withstand the harsh radiation environments experienced in outer space applications.